The present invention relates to an electronic device and a method for designing the same, more specifically an electronic device fabricated via the planarization step using CMP (Chemical Mechanical Polishing) and a method for designing the electronic device.
Electronic devices, such as semiconductor devices and magnetic heads, etc., use elements and interconnection structures of thin film layers. The fabrication of these elements often uses CMP method for planarizing the surfaces.
In the fabrication of semiconductor devices, for example, CMP is used in the step of forming the device isolation electrically isolating the elements formed on a semiconductor substrate, and in the step of forming the interconnection layers. That is, in the device isolation step using STI (Shallow Trench Isolation) method, CMP is used to planarize an insulating film which has been buried in trenches formed in the semiconductor substrate. Also in the interconnection forming step so called the damascene, CMP is used to planarize a conducting film which has been buried in trenches formed in an insulating film.
It is generally known that in the planarization by CMP, a surface state of an object to be polished influences characteristics of the CMP. For example, in a semiconductor device, the layout of patterns of the active regions, the interconnections, etc. influence characteristics of the CMP. This is due to the general properties of polishing, e.g., in a wide concave region, the polishing cloth tends to be deformed in polishing to cause excessive polishing of the film, and in a wide convex region, unpolished parts tend to take place at the central part.
The conventional methods for preventing layout of patterns from influencing the uniformity of the CMP are described in, e.g., Reference 1 (Japanese published unexamined patent application No. Hei 09-102539), Reference 2 (Japanese published unexamined patent application No. Hei 10-173035), Reference 3 (Japanese published unexamined patent application No. 2001-007114), and Reference 4 (Japanese published unexamined patent application No. 2003-347406).
Reference 1 discloses the method which, for the prevention of the generation of unpolished parts in a convex region, a buried material is etched with a mask having an inverted pattern of the trench pattern and then CMP is performed.
Reference 2 discloses the method which, for the prevention of concavities which are formed due to the density of convex patterns, active regions as dummy patterns are formed between active regions which are formed at a pitch of not less than 100 μm.
Reference 3 discloses the method which an area percentage of active regions present in a certain region is defined, whereby the uniformity of CMP is improved.
Reference 4 discloses the method which is an improvement of the method described in Reference 3 and which uses two windows of two different sizes to define area percentages of the active regions in chips. In the method described in Reference 4, an area percentage of active regions defined by the larger size window is made smaller than an area percentage defined by the smaller size window, whereby a layout of dense active regions is locally allowed, but active region are arranged less dense in a wide region.